There are several DAC architectures. The suitability of a DAC for a particular application is determined by following main parameters: physical size, power consumption, resolution, speed, accuracy and cost. Due to the complexity and the need for precisely matched components, DACs are mostly implemented as integrated circuits, short IC. Thus, DACs are a type of circuit used to interface digital systems, such as ASICs and FPGAs to analog circuits, frequently for the purpose of generating arbitrary waveforms or for digitally synthesizing a variety of signals.
A DAC converts an abstract finite-precision number, preferably a fixed-point binary number, into a physical quantity, preferably a voltage or a current. In particular, DACs are often used to convert finite-precision time series data to a continually varying physical signal.
There are known different techniques to convert a digital signal into an analog signal, e.g. a pulse-width modulator or oversampling DACs such as a delta-sigma DAC or R-2R ladder DACs, which are binary-weighted DACs that uses a repeating cascaded structure of resistor values R and 2R or successive approximation cyclic DACs, which successively construct the output during each cycle or thermometer-coded DACs and so on.
The technique, this invention refers to is a segmented current mode DAC, which contains unary coded electrical components for each digital level of the most significant bits, short MSB, and binary weighted electrical components for each least significant bit, short LSB, of the DAC connected to a summing unit. These precise voltages or currents sum to the correct output value. This is one of the fastest conversion methods but suffers from poor accuracy, because of the high precision required for each individual voltage or current and the needed time-alignment of the individual parallel components. Normally, those DACs have 8 or more analog output cells. Those binary weighted LSB DACs are for instance built as switched resistor DACs that contain a parallel resistor network. Alternatively, those binary weighted DACs are switched capacitor DACs that contain a parallel capacitor network.
The method described herein is based on a segmented current mode approach consisting of unary weighted MSB DAC and binary weighted LSB DAC that uses switched current sources, from which different current sources are selected based on the digital input. Such DACs are for instance known from US 2005/0258992 A1, U.S. Pat. No. 8,912,937 B2, U.S. Pat. No. 8,742,965 B1, U.S. Pat. No. 6,977,602 B1 and U.S. Pat. No. 6,476,748 B1.
These DACs receive digital inputs and produce analog outputs that are analog equivalences of the digital inputs in the form of currents or voltages. The DAC includes an encoder, a number of analog output cells and a summing circuit. An activated analog output cell generates a partial analog signal. The partial analog signals are then combined by a summing unit to produce an analog output, which is an analog representation of the digital input.
As per the Nyquist-Shannon sampling theorem, a DAC can reconstruct the original signal from the sampled data provided that its bandwidth meets certain requirements. Digital sampling introduces quantization error that manifests as low-level noise added to the reconstructed signal.
The DACs are typically made of a digital processing circuitry which drives a number of identical or matched analog unit circuits whose electrical outputs are combined in the summing unit to make the synthesized analog output signal. The arrangement of the identical or matched analog unit circuits is a combination of binary weighted and unary weighted analog circuit elements hereinafter referred to as analog output cells, whose properties are optimized for the output signal rate, output signal power and dynamic range.
For those DACs with sampling rates of tens of gigahertz, time glitches between the equivalent analog output cells within the DAC becomes a critical challenge to the DAC design. Those time glitches are mainly caused by mistiming of the partial analog signals at the output of the DAC. These glitches do not affect the final, settled value of the analog output signal for each digital input and appear only during the transition from one digital input to the next. Therefore, the time glitches corrupt the spectral content of the output signal, which presents an important concern for high-speed applications since the glitches can be misinterpreted as analog outputs.
In U.S. Pat. No. 6,812,878 B1, an analog output cell is shown comprising a current cell in series connection to one switching transistor and further in series connection to two clock transistors that provide the output signal of the cell. The clock transistors are driven by dedicated clock signals and thus are used as retiming latches to minimize the impact of time glitches in the final stage of each analog output switching unit of the appropriate analog output cell.
A drawback of such a structured analog output cell is that the output signal of the analog output cell is a return-to-zero signal, short RZ signal. This structure leads to the disadvantage that the effective RF output power is effectively cut in half, since the signal output is set to zero for half of the time. Additionally, no mixed-mode of the analog output cell can be obtained since the clock transistors are arranged at the analog output cell. Another drawback of such a structure is the fact that the data switching occurs before the retiming switching. This requires an active retiming switch while the data are settled. This leads to additional distortion on the signaling path.
Thus, there is a need to provide a DAC that overcomes the above-identified problems. Thus, a DAC is needed that comprises tighter phase noise performance and can operate at high speed and high dynamic ranges. The DAC should be used for RF power signals and no power wasting due to RZ signal outputs should be applied. The DAC should be less distorted. The DAC should operate with a high number of analog output cells.